The demand for higher capacity semiconductor memory devices has resulted in improved techniques to form memory devices and structures therein at higher levels of integration. However, because higher levels of integration typically require memory devices having smaller unit cell size, the area occupied by a cell capacitor in a memory device, such as a DRAM device, may have to be reduced significantly. As will be understood by those skilled in the art, this reduction in cell capacitor area can degrade memory cell performance at low voltages and adversely impact soft-error rate (SER) caused by α-particle radiation.
Conventional methods of increasing cell capacitor area include forming cell capacitor electrodes (e.g., storage electrodes) with hemispherical grain (HSG) silicon surface layers. For example, a conventional method of forming HSG silicon surface layers on cell capacitor electrodes is disclosed in U.S. Pat. No. 5,407,534 to Thakur. However, while capacitors having HSG surface layers therein (hereinafter “HSG capacitors”) have manifested enhanced capacitance in high density integrated circuits, HSG capacitors may lack stability and may incur performance degradation over the lifetime of an integrated circuit memory device. Studies have shown that the capacitance of a conventional HSG capacitor can vary greatly with respect to the polarity of a voltage applied across the capacitor's electrodes. In particular, when the voltage between the upper and lower electrodes of a HSG capacitor switches polarity from a positive value to a negative value and becomes reverse biased (during such operations as reading and writing operations), a significant drop in capacitance may be observed. For example, FIG. 2 illustrates a capacitance response curve of a conventional HSG capacitor when a voltage is applied across its upper and lower electrodes. As shown, the maximum capacitance (Cmax) is obtained when the potential difference across the electrodes is positive. Yet, when the potential difference is driven to a negative value, the capacitance gradually drops. In fact, at a negative value of −1.5V, the capacitance is at a minimum (Cmin), reaching only about 55% of Cmax.